From 42d8927734b68b58eec55039afd6ee0f3b74c1bd Mon Sep 17 00:00:00 2001
From: Michael Zuckerman <Michael.zuckerman@intel.com>
Date: Tue, 3 May 2016 14:26:52 +0000
Subject: [PATCH] [clang][AVX512][BuiltIn] Adding intrinsics for
cast{pd|ps|si}128_{pd|ps|si}512 and castsi256_si512 instruction set
Differential Revision: http://reviews.llvm.org/D19858
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@268387 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/Headers/avx512fintrin.h | 25 +++++++++++++++++++++++++
test/CodeGen/avx512f-builtins.c | 25 +++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/lib/Headers/avx512fintrin.h b/lib/Headers/avx512fintrin.h
index aca2364468c..7fa318129d9 100644
--- a/lib/Headers/avx512fintrin.h
+++ b/lib/Headers/avx512fintrin.h
@@ -343,6 +343,31 @@ _mm512_castps512_ps128(__m512 __a)
return __builtin_shufflevector(__a, __a, 0, 1, 2, 3);
}
+
+static __inline__ __m512d __DEFAULT_FN_ATTRS
+_mm512_castpd128_pd512 (__m128d __A)
+{
+ return __builtin_shufflevector( __A, __A, 0, 1, -1, -1, -1, -1, -1, -1);
+}
+
+static __inline__ __m512 __DEFAULT_FN_ATTRS
+_mm512_castps128_ps512 (__m128 __A)
+{
+ return __builtin_shufflevector( __A, __A, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_castsi128_si512 (__m128i __A)
+{
+ return __builtin_shufflevector( __A, __A, 0, 1, -1, -1, -1, -1, -1, -1);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_castsi256_si512 (__m256i __A)
+{
+ return __builtin_shufflevector( __A, __A, 0, 1, 2, 3, -1, -1, -1, -1);
+}
+
/* Bitwise operators */
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_and_epi32(__m512i __a, __m512i __b)
diff --git a/test/CodeGen/avx512f-builtins.c b/test/CodeGen/avx512f-builtins.c
index ffc54c747d4..47371ae0443 100644
--- a/test/CodeGen/avx512f-builtins.c
+++ b/test/CodeGen/avx512f-builtins.c
@@ -5588,3 +5588,28 @@ __m256i test_mm512_maskz_cvttpd_epu32(__mmask8 __U, __m512d __A) {
// CHECK: @llvm.x86.avx512.mask.cvttpd2udq.512
return _mm512_maskz_cvttpd_epu32(__U, __A);
}
+
+__m512d test_mm512_castpd128_pd512(__m128d __A) {
+ // CHECK-LABEL: @test_mm512_castpd128_pd512
+ // CHECK: shufflevector <2 x double> %1, <2 x double> %2, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ return _mm512_castpd128_pd512(__A);
+}
+
+__m512 test_mm512_castps128_ps512(__m128 __A) {
+ // CHECK-LABEL: @test_mm512_castps128_ps512
+ // CHECK: shufflevector <4 x float> %1, <4 x float> %2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ return _mm512_castps128_ps512(__A);
+}
+
+__m512i test_mm512_castsi128_si512(__m128i __A) {
+ // CHECK-LABEL: @test_mm512_castsi128_si512
+ // CHECK: shufflevector <2 x i64> %1, <2 x i64> %2, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ return _mm512_castsi128_si512(__A);
+}
+
+__m512i test_mm512_castsi256_si512(__m256i __A) {
+ // CHECK-LABEL: @test_mm512_castsi256_si512
+ // CHECK: shufflevector <4 x i64> %1, <4 x i64> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+ return _mm512_castsi256_si512(__A);
+}
+
--
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