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r322030 | rsmith | 2018-01-08 13:46:42 -0800 (Mon, 08 Jan 2018) | 3 lines

PR35862: Suppress -Wmissing-variable-declarations warning on inline variables,
variable templates, and instantiations thereof.

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r333497 | ctopper | 2018-05-29 20:38:15 -0700 (Tue, 29 May 2018) | 5 lines

[X86] Fix the names of a bunch of icelake intrinsics.

Mostly this fixes the names of all the 128-bit intrinsics to start with _mm_ instead of _mm128_ as is the convention and what the Intel docs say.

This also fixes the name of the bitshuffle intrinsics to say epi64 for 128 and 256 bit versions.
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r326476 | mstorsjo | 2018-03-01 12:22:57 -0800 (Thu, 01 Mar 2018) | 7 lines

[RecordLayout] Only assert that fundamental type sizes are power of two on MSVC

Make types with sizes that aren't a power of two an error (that can
be disabled) in structs with ms_struct layout, except on mingw where
the situation is quite likely to occur and GCC handles it silently.

Differential Revision: https://reviews.llvm.org/D43908
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r326173 | mstorsjo | 2018-02-26 22:27:06 -0800 (Mon, 26 Feb 2018) | 17 lines

[RecordLayout] Don't align to non-power-of-2 sizes when using -mms-bitfields

When targeting GNU/MinGW for i386, the size of the "long double" data
type is 12 bytes (while it is 8 bytes in MSVC). When building
with -mms-bitfields to have struct layouts match MSVC, data types
are laid out in a struct with alignment according to their size.
However, this doesn't make sense for the long double type, since
it doesn't match MSVC at all, and aligning to a non-power-of-2
size triggers other asserts later.

This matches what GCC does, aligning a long double to 4 bytes
in structs on i386 even when -mms-bitfields is specified.

This fixes asserts when using the max_align_t data type when
building for MinGW/i386 with the -mms-bitfields flag.

Differential Revision: https://reviews.llvm.org/D43734
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r326235 | mstorsjo | 2018-02-27 11:42:19 -0800 (Tue, 27 Feb 2018) | 6 lines

[MinGW, CrossWindows] Allow passing -static together with -shared

In these combinations, link a DLL as usual, but pass -Bstatic instead
of -Bdynamic to indicate prefering static libraries.

Differential Revision: https://reviews.llvm.org/D43811
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r329300 | manojgupta | 2018-04-05 08:29:52 -0700 (Thu, 05 Apr 2018) | 16 lines

Disable -fmerge-all-constants as default.

Summary:
"-fmerge-all-constants" is a non-conforming optimization and should not
be the default. It is also causing miscompiles when building Linux
Kernel (https://lkml.org/lkml/2018/3/20/872).

Fixes PR18538.

Reviewers: rjmccall, rsmith, chandlerc

Reviewed By: rsmith, chandlerc

Subscribers: srhines, cfe-commits

Differential Revision: https://reviews.llvm.org/D45289
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r330331 | erichkeane | 2018-04-19 07:27:05 -0700 (Thu, 19 Apr 2018) | 14 lines

Fix __attribute__((force_align_arg_pointer)) misalignment bug

The force_align_arg_pointer attribute was using a hardcoded 16-byte
alignment value which in combination with -mstack-alignment=32 (or
larger) would produce a misaligned stack which could result in crashes
when accessing stack buffers using aligned AVX load/store instructions.

Fix the issue by using the "stackrealign" function attribute instead
of using a hardcoded 16-byte alignment.

Patch By: Gramner

Differential Revision: https://reviews.llvm.org/D45812

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r330926 | sepavloff | 2018-04-25 23:28:47 -0700 (Wed, 25 Apr 2018) | 9 lines

[ConfigFiles] Update argument strings when merging argrument lists

Implementation of `InputArgList` assumes its field `ArgStrings` contains
strings for each argument exactly in the same order. This condition was
broken when arguments from config file and from invocation were merged.

This change fixes https://bugs.llvm.org/show_bug.cgi?id=37196 (Clang
config files can crash argument handling).

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r325446 | dim | 2018-02-17 13:04:35 -0800 (Sat, 17 Feb 2018) | 28 lines

[X86] Add 'sahf' CPU feature to frontend

Summary:
Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the
`+sahf` feature for the backend, for bug 36028 (Incorrect use of
pushf/popf enables/disables interrupts on amd64 kernels).  This was
originally submitted in bug 36037 by Jonathan Looney
<jonlooney@gmail.com>.

As described there, GCC also uses `-msahf` for this feature, and the
backend already recognizes the `+sahf` feature. All that is needed is to
teach clang to pass this on to the backend.

The mapping of feature support onto CPUs may not be complete; rather, it
was chosen to match LLVM's idea of which CPUs support this feature (see
lib/Target/X86/X86.td).

I also updated the affected test case (CodeGen/attr-target-x86.c) to
match the emitted output.

Reviewers: craig.topper, coby, efriedma, rsmith

Reviewed By: craig.topper

Subscribers: emaste, cfe-commits

Differential Revision: https://reviews.llvm.org/D43394

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r327322 | arphaman | 2018-03-12 12:36:29 -0700 (Mon, 12 Mar 2018) | 7 lines

[Tooling] Clear the PreambleSrcLocCache when preamble is discarded during reparsing

This ensures that diagnostics are not remapped to incorrect preamble locations after
the second reparse with a remapped header file occurs.

rdar://37502480

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r325651 | sdardis | 2018-02-21 00:05:05 +0000 (Wed, 21 Feb 2018) | 34 lines

[mips] Spectre variant two mitigation for MIPSR2

This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It provides the option
-mindirect-jump=hazard, which instructs the LLVM backend to replace
indirect branches with their hazard barrier variants.

This option is accepted when targeting MIPS revision two or later.

The migitation strategy suggested by MIPS for these processors is to
use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.

These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.

These instructions are used with the option -mindirect-jump=hazard
when branching indirectly and for indirect function calls.

These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.

Implementation note: I've opted to provide this as an
-mindirect-jump={hazard,...} style option in case alternative
mitigation methods are required for other implementations of the MIPS
ISA in future, e.g. retpoline style solutions.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D43487

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r328829 | manojgupta | 2018-03-29 14:11:15 -0700 (Thu, 29 Mar 2018) | 23 lines

[AArch64]: Add support for parsing rN registers.

Summary:
Allow rN registers to be simply parsed as correspoing xN registers.
The "register ... asm("rN")" is an command to the
compiler's register allocator, not an operand to any individual assembly
instruction. GCC documents this syntax as "...the name of the register
that should be used."

This is needed to support the changes in Linux kernel (see
https://lkml.org/lkml/2018/3/1/268 )

Note: This will add support only for the limited use case of
register ... asm("rN"). Any other uses that make rN leak into assembly
are not supported.

Reviewers: kristof.beyls, rengolin, peter.smith, t.p.northover

Reviewed By: peter.smith

Subscribers: javed.absar, eraman, cfe-commits, srhines

Differential Revision: https://reviews.llvm.org/D44815
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r327099 | rsmith | 2018-03-08 18:00:01 -0800 (Thu, 08 Mar 2018) | 3 lines

PR36645: Go looking for an appropriate array bound when constant-evaluating a
name of an array object.

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r324308 | rtrieu | 2018-02-06 03:58:21 +0100 (Tue, 06 Feb 2018) | 4 lines

Fix crash on invalid.

Don't call a method when the pointer is null.

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r325655 | ctopper | 2018-02-21 01:16:50 +0100 (Wed, 21 Feb 2018) | 8 lines

[X86] Disable CLWB in Cannon Lake

Cannon Lake does not support CLWB, therefore it
does not include all features listed under SKX.

Patch by Gabor Buella

Differential Revision: https://reviews.llvm.org/D43459
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r325576 | hans | 2018-02-20 13:43:02 +0100 (Tue, 20 Feb 2018) | 13 lines

Revert r325375 "[MS] Make constexpr static data members implicitly inline"

This broke Clang bootstrap on Windows, PR36453.

> This handles them exactly the same way that we handle const integral
> static data members with inline definitions, which is what MSVC does.
>
> As a follow-up, now that we have a way to mark variables inline in the
> AST, we should consider marking them implicitly inline there instead of
> only treating them as inline in CodeGen. Unfortunately, this breaks a
> lot of dllimport test cases, so that is future work for now.
>
> Fixes PR36125.
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r325375 | rnk | 2018-02-16 20:44:47 +0100 (Fri, 16 Feb 2018) | 11 lines

[MS] Make constexpr static data members implicitly inline

This handles them exactly the same way that we handle const integral
static data members with inline definitions, which is what MSVC does.

As a follow-up, now that we have a way to mark variables inline in the
AST, we should consider marking them implicitly inline there instead of
only treating them as inline in CodeGen. Unfortunately, this breaks a
lot of dllimport test cases, so that is future work for now.

Fixes PR36125.
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r323998 | rsmith | 2018-02-01 21:01:49 +0100 (Thu, 01 Feb 2018) | 5 lines

PR36157: When injecting an implicit function declaration in C89, find the right
DeclContext rather than injecting it wherever we happen to be.

This avoids creating functions whose DeclContext is a struct or similar.

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PACXXABI now takes the host ABI for code generation / new Calling Convention / allow invoke generation when compiling with -pacxx

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r324537 | rsmith | 2018-02-07 23:25:16 +0100 (Wed, 07 Feb 2018) | 14 lines

PR36055: fix computation of *-dependence in nested initializer lists.

When we synthesize an implicit inner initializer list when analyzing an outer
initializer list, we add it to the outer list immediately, and then fill in the
inner list. This gives the outer list no chance to update its *-dependence bits
with those of the completed inner list. To fix this, re-add the inner list to
the outer list once it's completed.

Note that we do not recompute the *-dependence bits from scratch when we
complete an outer list; this would give the wrong result for the case where a
designated initializer overwrites a dependent initializer with a non-dependent
one. The resulting list in that case should still be dependent, even though all
traces of the dependence were removed from the semantic form.

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r324594 | aivchenk | 2018-02-08 12:15:21 +0100 (Thu, 08 Feb 2018) | 17 lines

Fix for #31362 - ms_abi is implemented incorrectly for values >=16 bytes.

Summary:
This patch is a fix for following issue:
https://bugs.llvm.org/show_bug.cgi?id=31362 The problem was caused by front end
lowering C calling conventions without taking into account calling conventions
enforced by attribute. In this case win64cc was no correctly lowered on targets
other than Windows.

Reviewed By: rnk (Reid Kleckner)

Differential Revision: https://reviews.llvm.org/D43016

Author: belickim <mateusz.belicki@intel.com>



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r324514 | arphaman | 2018-02-07 21:45:39 +0100 (Wed, 07 Feb 2018) | 10 lines

[PR36008] Avoid -Wsign-compare warning for enum constants in
typeof expressions

This commit looks through typeof type at the original expression when diagnosing
-Wsign-compare to avoid an unfriendly diagnostic.

rdar://36588828

Differential Revision: https://reviews.llvm.org/D42561

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r324419 | vsapsai | 2018-02-06 23:39:25 +0100 (Tue, 06 Feb 2018) | 23 lines

[Lex] Fix handling numerical literals ending with ' and signed exponent.

For input `0'e+1` lexer tokenized as numeric constant only `0'e`. Later
NumericLiteralParser skipped 0 and ' as digits and parsed `e+1` as valid
exponent going past the end of the token. Because it didn't mark numeric
literal as having an error, it continued parsing and tried to expandUCNs
with StringRef of length -2.

The fix is not to parse exponent when we reached the end of token.

Discovered by OSS-Fuzz:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4588

rdar://problem/36076719

Reviewers: rsmith, t.p.northover

Reviewed By: rsmith

Subscribers: cfe-commits, jkorous-apple

Differential Revision: https://reviews.llvm.org/D41834

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added __PACXX_FUNCTION__ keyword / MangleContext is now owned by ASTContext to get consistent lambda IDs

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r324439 | compnerd | 2018-02-07 02:55:08 +0100 (Wed, 07 Feb 2018) | 5 lines

AST: support SwiftCC on MS ABI

Microsoft has reserved the identifier 'S' as the swift calling
convention.  Decorate the symbols appropriately.  This enables swift on
Windows.
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r324246 | mzeren-vmw | 2018-02-05 16:59:00 +0100 (Mon, 05 Feb 2018) | 33 lines

[clang-format] Re-land: Fixup #include guard indents after parseFile()

Summary:
When a preprocessor indent closes after the last line of normal code we do not
correctly fixup include guard indents. For example:

  #ifndef HEADER_H
  #define HEADER_H
  #if 1
  int i;
  #  define A 0
  #endif
  #endif

incorrectly reformats to:

  #ifndef HEADER_H
  #define HEADER_H
  #if 1
  int i;
  #    define A 0
  #  endif
  #endif

To resolve this issue we must fixup levels after parseFile(). Delaying
the fixup introduces a new state, so consolidate include guard search
state into an enum.

Reviewers: krasimir, klimek

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D42035
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r323904 | mzeren-vmw | 2018-01-31 21:05:50 +0100 (Wed, 31 Jan 2018) | 34 lines

[clang-format] Align preprocessor comments with #

Summary:
r312125, which introduced preprocessor indentation, shipped with a known
issue where "indentation of comments immediately before indented
preprocessor lines is toggled on each run". For example these two forms
toggle:

  #ifndef HEADER_H
  #define HEADER_H
  #if 1
  // comment
  #   define A 0
  #endif
  #endif

  #ifndef HEADER_H
  #define HEADER_H
  #if 1
     // comment
  #   define A 0
  #endif
  #endif

This happens because we check vertical alignment against the '#' yet
indent to the level of the 'define'. This patch resolves this issue by
aligning against the '#'.

Reviewers: krasimir, klimek, djasper

Reviewed By: krasimir

Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D42408
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r324059 | mstorsjo | 2018-02-02 07:22:35 +0100 (Fri, 02 Feb 2018) | 21 lines

[MinGW] Emit typeinfo locally for dllimported classes without key functions

This fixes building Qt as shared libraries with clang in MinGW
mode; previously subclasses of the QObjectData class (in other
DLLs than the base DLL) failed to find the typeinfo symbols
(that neither were emitted in the base DLL nor in the DLL
containing the subclass).

If the virtual destructor in the newly added testcase wouldn't
be pure (or if there'd be another non-pure virtual method),
it'd be a key function and things would work out even before this
change. Make sure to locally emit the typeinfo for these classes
as well.

This matches what GCC does in this specific testcase.

This fixes the root issue that spawned PR35146. (The difference
to GCC that is initially described in that bug still is present
though.)

Differential Revision: https://reviews.llvm.org/D42641
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r323935 | rsmith | 2018-02-01 01:28:36 +0100 (Thu, 01 Feb 2018) | 5 lines

PR36181: Teach CodeGen to properly ignore requests to emit dependent entities.

Previously, friend function definitions within class templates slipped through
the gaps and caused the MS mangler to assert.

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r324134 | ericwf | 2018-02-02 21:30:39 +0100 (Fri, 02 Feb 2018) | 14 lines

Make __has_unique_object_representations reject empty union types.

Summary:
Clang incorrectly reports empty unions as having a unique object representation. However, this is not correct since `sizeof(EmptyUnion) == 1` AKA it has 8 bits of padding. Therefore it should be treated the same as an empty struct and report `false`.

@erichkeane also suggested this fix should be merged into the 6.0 release branch, so the initial release of `__has_unique_object_representations` is as bug-free as possible. 

Reviewers: erichkeane, rsmith, aaron.ballman, majnemer

Reviewed By: erichkeane

Subscribers: cfe-commits, erichkeane

Differential Revision: https://reviews.llvm.org/D42863
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r323155 | chandlerc | 2018-01-22 23:05:25 +0100 (Mon, 22 Jan 2018) | 133 lines

Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..

Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html

The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.

The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.

However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.

On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.

This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886

We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
  __llvm_external_retpoline_r11
```
or on 32-bit:
```
  __llvm_external_retpoline_eax
  __llvm_external_retpoline_ecx
  __llvm_external_retpoline_edx
  __llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.

There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.

The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.

For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.

When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.

When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.

However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.

We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.

This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.

Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer

Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D41723
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r323360 | kparzysz | 2018-01-24 19:42:19 +0100 (Wed, 24 Jan 2018) | 2 lines

[Hexagon] Accept lowercase b in -hvx-length=64b and -hvx-length=128b

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r323485 | aemerson | 2018-01-26 01:27:22 +0100 (Fri, 26 Jan 2018) | 3 lines

[Driver] Add an -fexperimental-isel driver option to enable/disable GlobalISel.

Differential Revision: https://reviews.llvm.org/D42276
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r322245 | ctopper | 2018-01-11 02:37:59 +0100 (Thu, 11 Jan 2018) | 5 lines

[X86] Make -mavx512f imply -mfma and -mf16c in the frontend like it does in the backend.

Similarly, make -mno-fma and -mno-f16c imply -mno-avx512f.

Withou this  "-mno-sse -mavx512f" ends up with avx512f being enabled in the frontend but disabled in the backend.
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